Freescale embraces IMEC multiprocessor approach

Peter Clarke
(10/05/2004 8:45 AM EDT)

  LEUVEN, Belgium — In the hope of establishing its own proprietary hardware-software platform for future mobile electronics applications, Freescale Semiconductor Inc. has signed up to perform collaborative research with IMEC on reconfigurable multiprocessor systems.

The research is based around IMEC's hybrid reconfigurable VLIW multiprocessor architecture, which was disclosed in April 2004. The work is being done under an IMEC Industrial Affiliation Program (IIAP) but neither the duration of the collaboration nor any timetable were disclosed.

The IMEC architecture, along with seeking to obtain great energy efficiency than other approaches, traditionally an IMEC and European focus, is designed to be programmable in C, eliminating the need to hand-code tasks for the processing array.

Numerous companies and research teams have tried to create software programmable parallel processing systems but the mix of inherent internal complexity, a lack of generality and numerous compilation problems, have thwarted most.

"The combination of Freescale's microprocessor know-how and insight into requirements of embedded systems applications, combined with IMEC's expertise in reconfigurable architectures and system design, makes this collaboration a win-win endeavor," said Rudy Lauwereins, vice-president of Design Technology for Integrated Information and Communication Systems at IMEC, in a statement.

"IMEC's technology will complement Freescale's long-standing technology position in wireless SoC design and provide our customers with innovative and disruptive semiconductor solutions," said Ken Hansen, senior technical fellow and director of advanced technology for Freescale's wireless group, in the same statement.

IMEC's processor architecture template combines VLIW processors and coarse-grain reconfigurable hardware. A C compiler is developed along with the template, which maps applications to the hardware aand should allow a fast design cycle while maintaining performance metrics achieved by a particular new architecture