VMETRO simplifies development of embedded DSP systems with FPGA development kit
July 22, 2008 -- Today VMETRO announced the FusionXF FPGA development kit. FusionXF is targeted at reducing the design time and optimizing the performance of complex FPGA and PowerPC processing systems. It aids customers in the development of their FPGA algorithms and logic for VMETRO’s customer-programmable FPGA products. While FusionXF is very useful for a single FPGA design, it is invaluable in larger embedded real-time DSP system designs where there is a need to integrate and move data between multiple distributed FPGAs and processors.
FusionXF includes FPGA HDL functions, software APIs, drivers, utilities, example designs, and documentation to simplify the task of integrating FPGAs into an embedded real-time DSP system design. It provides the building blocks to build a fully functional FPGA design that a customer can easily integrate their FPGA algorithms and logic into. Additionally, FusionXF enables the control and utilization of FPGA resources from PowerPC processors and efficient data streaming within a single FPGA and between processors and FPGAs in a system. With the core functionality and glue logic to create a fully functional FPGA design provided by FusionXF, valuable project time can be spent implementing application specific functionality, e.g., optimizing computational algorithms.
Developers can integrate the VMETRO developed FusionXF functions directly into their application or modify the HDL and software libraries, drivers, and example designs to fit their unique need. FusionXF is designed to consume minimum FPGA logic and resources. Only the HDL functions required by the customer’s application need to be included in an FPGA design leaving the maximum amount of FPGA resources available for the user’s algorithms and logic. FusionXF is currently supported on VMETRO’s VPF2 (VXS) and HPE640 (VPX) hybrid PowerPC and FPGA boards, FPE650 quad-FPGA VPX board, and AD1500 and AD3000 A/D XMC/PMC modules.
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- CAN-FD Controller
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- OpenHW Group Announces Tape Out of RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software
- Microchip FPGAs Speed Intelligent Edge Designs and Reduce Development Cost and Risk with Tailored PolarFire® FPGA and SoC Solution Stacks
- Rambus Demonstrates CXL Platform Development Kit at SC23
- Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers
Latest News
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development