The fabless-foundry model will survive (at least through 14-nm)
Handel Jones, International Business Strategies Inc.,
EETimes (6/15/2012 6:59 PM EDT)
Editor's note: This article was rewritten in rebutal to comments made in April by Mark Bohr, an Intel Senior Fellow. As reported by EE Times, Bohr said the fabless-foundry model is"collapsing."
What are the problems?
1. Parametric yields at 28 nm are not at expected levels. Process variables such as random dopant fluctuations, line width and line gap variations, and via resistance, which affect RC-related timing issues, result in both unpredictable and low parametric yields for the targeted specifications. The process variables have increasing impact on leakage, power consumption and yields.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related News
- TSMC Selects Legend's Model Diagnoser for Standard Cell Library Quality Assurance
- HDL Design House announces AT25DF161 VITAL behavioral model
- Carbon Design Systems Adds Co-Simulation Model Library to Expanding System-Level Validation Tool Suite
- Carbon Automates AXI Interconnect Model Creation
Latest News
- AI Directs UFS Advancement
- Qualitas Semiconductor Expands Automotive Momentum with 5nm IP Bundle Agreement
- Cyient Semiconductors Acquires Majority Stake in Kinetic Technologies to Drive Custom Power IC Leadership for Edge AI and High-Performance Compute Markets
- Rivian Unveils Custom Silicon, Next-Gen Autonomy Platform, and Deep AI Integration
- NanoXplore raises €20 million from MBDA and Bpifrance to accelerate its diversification into defense and its growth in support of European strategic sovereignty