EZchip offers 10-Gbit traffic manager as chip, core

EZchip offers 10-Gbit traffic manager as chip, core
By Robert Keenan, CommsDesign.com
January 8, 2003 (11:07 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030108S0018

SAN JOSE, Calif. — One-year after announcing the availability of its NP-1 network processor, EZchip Technologies is sending its first 10-Gbit/second traffic manager to market for OEM designs. The fabless chip developer is also offering the traffic manager as an intellectual property (IP) core that can be implemented on a field-programmable gate array.

The QX-1 traffic manager is designed to work in conjunction with the NP-1 network processor. It could "theoretically" operate as a standalone part in system designs, "but we're not focusing there," said Eli Futcher, president and chief executive officer of EZchip.

By closely matching its network processor and traffic manager, EZchip hopes to optimize the movement of data through the data path, Futcher said. The NP-1 can define data, make forwarding decisions and classify its flow while the traffic manager handle tasks such as queuing, congestion management, per-flow queuing and hier archical scheduling, he said.

The QX-1 supports a host of interfaces on the fabric and system side. Designers using this part can connect to a switch fabric using either a CSIX or SPI 4.2-based streaming interface. Designers can link up with framers or Ethernet multiplexers using either a 10-Gigabit Ethernet interface, an OC-192 interface, four OC-48 interfaces, 16 OC-12 interfaces or 16 Gigabit Ethernet interfaces.

Despite the variety of I/O options, designers may still want different interfaces. To accommodate them, Futcher said EZchip will license an IP core version of the QX-1 for use on Xilinx Inc.'s Virtex FPGAs.

The QX-1 is sampling now priced at $695 each in 10,000-unit quantities. Pricing for the QX-1 core involves a $50,000 one-time fee and a $50 per-copy fee.