eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019
New software maps high-level AI workloads to eSilicon’s neuASIC modular AI ASIC IP platform
August 15, 2019 -- San Jose, Calif. -- eSilicon, an independent provider of FinFET-class ASIC design, market-specific IP platforms and advanced 2.5D packaging solutions, will exhibit at Hot Chips 31.
eSilicon at Hot Chips 31
Introducing AI Accelerator Software
eSilicon’s 7nm FinFET neuASIC™ AI IP platform is a library of AI-specific tiles that can be configured to support an AI algorithm. eSilicon’s new AI Accelerator maps high-level AI workloads to the neuASIC platform and estimates PPA (power, performance, area) for the algorithm in the resultant silicon implementation.
neuASIC IP plus the AI Accelerator software allow design exploration of candidate architectures to ensure the design will be within the target specifications. This approach supports changes to the algorithm or the package.
eSilicon will be demonstrating AI Accelerator on Monday and Tuesday at its sponsor table.
AI Accelerator is available in IP Navigator, eSilicon’s IP exploration and evaluation tool, at no charge. A free eSilicon STAR account is required to access Navigator, which may be requested here.
Update on Chiplets
The idea of chiplets makes sense in terms of yield, cost and risk, but they haven’t really caught on. Is there a chiplet business model that works?
When & Where
Sunday-Tuesday, August 18-20, 2019
Memorial Auditorium, Stanford Campus
Palo Alto, California
Registration for the conference is still open online or on site during the event at the registration booth.
About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- CXL 3.0 Controller
- ECC7 Elliptic Curve Processor for Prime NIST Curves
Related News
- AI Hardware Summit 2019: Booth-to-Booth eSilicon 58G DSP-Based SerDes Demonstration Over a Five-Meter Samtec Copper Cable
- ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies
- GlobalFoundries and MIT Collaborate to Advance Research and Innovation on Essential Chips for AI
- InPsytech Joins Intel Foundry Accelerator IP Alliance to Boost HPC, AI, And Automotive Applications
Latest News
- AIStorm and DB HiTek Debut SpectroMic™ KWS—an 18uA Always-on Keyword-Spotting Solution Enabling IoT AI Voice Interaction
- SignatureIP Unveils Industry-Leading CXL 3.2 Solution for High-Performance Computing
- Synopsys and Ansys Provide Update Regarding Expected Timing of Acquisition Close
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards