Duolog releases SDRAM, DDR2 and NAND Flash sMEM synthesisable memory models to allow functional system validation in a simulation or emulation environment
-- Duolog Technologies, a leading provider of SoC flow automation intellectual property and design services for the communications semiconductor market, today announced the availability of its SDRAM, DDR2 and NAND Flash memory models to assist functional system verification in a simulation or emulation environment.
The SDRAM and DDR2 memory models are fully cycle accurate with a full command interpreter from initialization sequences to refreshes A core finite state machine implementation supports full memory functionality and facilitates logic validation and debug of command sequences, bank accesses and refresh sequences. a full command interpreter and support configurable memory size and data width.
The models work out of the box on a wide range of emulation environments from custom emulation (Xilinx/Altera) systems to industry standard emulators.
“Any technology which eases the accelleration and emulation of system-level validation is very valuable at the moment.”, commented Dave Murray, “Some of our customers are utilizing these models to do full system-level validation by loading extensive validation programs into the models and running test suites in their target environments. As these models integrate easily into standard simulation and emulation environments, this significantly reduces system verification times and time to market for SoC platforms”.
About Duolog
Duolog Technologies has offices in Dublin & Galway (Ireland) and in Budapest, Hungary. Duolog is a leading supplier of intellectual property, ESL tools and methodology services in the areas of Wired and Wireless Broadband Communications. The company is developing market leading SoC flow design and verification solutions and wireless intellectual property. Duolog also offers hardware and software design services. Further information is available at www.duolog.com
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Breker Verification Systems Unifies SoC Verification Across Simulation, Acceleration, In-Circuit Emulation, FPGA Prototyping, Silicon Validation
- Real Intent Awarded U.S. Patent for Methods and Systems for Correcting X-pessimism in Gate-level Simulation or Emulation
- Samsung Develops Industry's First System-in-Package (SiP) with an ARM-based processor, NAND flash and SDRAM
- 0-In Delivers EDA Industry’s First PCI Express Verification IP for Simulation, Formal Verification and Hardware Acceleration and Emulation
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack