DSP center spurs QuickLogic system-chip plans

DSP center spurs QuickLogic system-chip plans
By Rick Merritt, EE Times
August 9, 2000 (6:05 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000809S0031

SAN JOSE, Calif. — QuickLogic Corp. has tipped plans to set up the first of a series of design centers in an effort to bolster its emerging business in standard products that merge FPGA blocks with intellectual-property cores. The company will establish a 20-person DSP design center in Dallas before the end of September, said chief executive officer E. Thomas Hart.

The center is intentionally situated in the backyard of DSP giant Texas Instruments Inc. in an effort to ease the job of recruiting skilled DSP designers. The center also plans to reach out to customers in the hotbed of telecom systems companies — such as Alcatel, Cisco, Ericsson and Nokia — in the nearby Telecom Corridor region surrounding Richardson, Texas.

"If you look at what is happening in the Dallas area around these big companies, you will see there are a lot of interesting startups forming," said Hart. "We want to open up a number of world-class design centers in these sorts of areas where there is a lot of activity centered around key applications."

The move is part of a larger attempt by Hart to push QuickLogic, a relatively small maker of programmable-logic devices, toward what he believes is an emerging market for standard programmable parts. The company is rolling out a series of products that merge its FPGA cores with a standard-product core. These include the QuickDSP, QuickPCI and QuickFC parts, which respectively blend an FPGA with a DSP coprocessor, PCI controller and Fibre Channel controller.These parts, some of which are still in the design phase, now account for less than 10 percent of the company's roughly $50 million in annual revenues. But Hart believes the family, which he dubs "embedded standard products" (ESPs), will make up as much as 50 percent of the company's business within three years.

Specifically, QuickLogic estimates this new ESP business could grow from $4 million last year to $1.3 billion in 2004. That's significant given tha t the entire FPGA market in which QuickLogic now plays is expected to hit just $3.5 billion in 2004.

Thus the company's strategy, as forged by Hart, is not to go head to head with much larger FPGA makers Xilinx Inc. and Altera Corp., but to sidestep those giants in a race to the new market of merged FPGAs and intellectual-property cores. "This is our opportunity to lose," Hart said.

The design centers will play a key role in this business shift. While FPGAs can be sold to engineers based on specs in a data sheet, the ESP parts cannot. QuickLogic considers its initial line as subsystems parts which are more of a strategic sell to top engineering managers, Hart said. But the next step is trickier.

Strategic cores

In April, the company cut a licensing deal with MIPS Technologies Inc. that will bring the 32- and 64-bit versions of the MIPS microprocessor onto a merged MIPS-FPGA part. QuickLogic plans to hammer out a series of application-specific parts using a MIPS core, an FPGA bloc k and surrounding logic that supports a targeted market. It also plans to license a second major processor core that will be the basis for a similar family of parts to be announced in October.

"These will be parts aimed at very different markets such as 3G basestations or terabit routers," said Hart, speaking of the QuickMIPS and the unannounced product family. "We are targeting the infrastructure — basestations, network-attached storage and servers — not PCs or handsets."

The systems expertise needed to craft such application-specific designs will emerge from the new design centers. The goal is for these centers to draw together QuickLogic designers and engineers from contract design firms and from potential customers to craft designs that can meet a particular company's need and be resold as a standard part.

Hart would not comment on how many such centers in what sorts of application areas or geographies QuickLogic plans. However, he noted that the company is sitting on about $75 mil lion in cash and will look to acquire small (10-to-20 person) design firms as a quick way to establish a presence in centers of design excellence.

The new business in standard programmable parts is driven, in part, by the rising cost of ASICs, Hart said. "While [LSI Logic chairman] Wilf Corrigan may have run 10 lots a year for you in the past, he will not do that in a world of 0.15-micron designs on 300-mm wafers," Hart said. "The same trends in high mask costs, process complexity and wafer sizes that are driving up ASIC costs will also drive customers to standard products based on FPGAs."

QuickLogic is not alone in seeing this opportunity. Xilinx recently licensed the PowerPC, and Altera plans to use MIPS, ARM and ultimately the PowerPC as part of a similar drive. Whether the relatively small QuickLogic can outmaneuver its larger competitors in this hybrid FPGA/core business remains to be seen.

However, Hart said that QuickLogic is taking a fundamentally different view of the opportunity. While Altera talks of a system-on-a-programmable-chip, using a system-on-chip model, QuickLogic is chasing a model more like that of the application-specific standard product (ASSP).

"We will provide a complete systems solution," said Hart. "The really high-end stuff here is like an ASSP. In that way, we are moving from providing components to subsystems to full systems-level solutions."

Observers noted that one weakness in the QuickLogic plan is that to date it focuses on combining a single core with an FPGA block. Analysts believe that the emerging market will call for multiple cores merged with an FPGA in what Dataquest Inc. has called an application-specific programmable platform device (ASPP).

"I think the concept [of an ASPP] is a good one," said Richard Wawrzyniak, a senior market analyst at Semico Research's office in Irvine, Calif. "Success in this area all comes down to cost, time-to-market and the ease of reconfiguring the device for t he next product.

"My question is, how many times will you be able to turn such a programmable part for the next design?"

Wawrzyniak added, "My gut tells me you might be able to reconfigure the part once or twice, but that will be about it," before the market moves on. "The whole thing really revolves around time-to-market. By contrast, the formal system-on-chip approach can take months and months, and you can miss the market window you are targeting."