Domain Specific Accelerators Will Drive Vector Processing on RISC-V

By Charlie Cheng, Andes Technology (May 26, 2020)

When the RISC-V market first began, the initial rush was to cost reduce designs that would have otherwise used proprietary CPU instruction set architectures (ISAs) in deeply embedded applications. When these systems on chips (SoCs) began being fabricated in FinFET semiconductor process technology, the mask costs grew so expensive that many finite state machines were replaced with programmable micro sequencers based on the RISC-V instruction set. These created the initial excitement and later on the commoditization of simple RISC-V cores from 2014 to 2018.

As the RISC-V architecture became more mature and SoC designers became familiar with the ISA, it found adoption in real-time applications that demanded high performance: in particular, serving as a front end to highly specialized acceleration engines for applications such as artificial intelligence. One key reason for this adoption is that RISC-V is an open architecture for users to add instructions, so the RISC-V processors did not have to treat the accelerators as memory-mapped I/O devices, as was the case for traditional architectures. Instead, they can use a low-latency co-processor.

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