'Divide and conquer' with verification IP (by Kevin Silver, Denali Software)

Kevin Silver
(08/13/2004 3:00 PM EDT)

  As design complexity and simulator capacity increase, verification and testbench complexity grow exponentially. Languages such as SystemC and SystemVerilog enable designers to work at a higher level of abstraction, and capture design intent along with the design.

Clearly, languages are the right answer for describing and verifying application-specific designs. That is, the "special sauce" that is everything but the processor, bus, and interface IP blocks. But this doesn't offer the big productivity improvement needed for functional verification. The biggest opportunity today comes in the form of verification IP for standard chip interfaces.

Designs in every industry segment are built around standard interfaces. You can't find a complex chip that does not have some sort of standard interface. Unfortunately, for design and verification teams, these standards are all described in documents, many in the 500+ page range, containing ambiguities subject to human interpretation. To make things even more complex, most implementations of these interfaces are different. The PCI Express standard, for example, allows for a wide range of device types, features and functionality.

No chip designs are implementing 100 percent of the features defined in the specification. This is true of even the most standardized interfaces, such as DDR memory where each device adheres to a standard. Most vendors add in differentiating features and functionality that cannot be ignored for functional verification.

Creating models, assertions, compliance suites and application traffic for these interfaces is a tremendous task. Design managers agree that it is not practical to invest in becoming an expert in developing verification IP for these interfaces.

In the true sense of divide and conquer, verification IP is rapidly emerging as a necessary element of the functional verification environment, especially for complex chip interfaces. Verification IP vendors are able to leverage specific domain knowledge for these interfaces, along with verification expertise to provide value to chip designers.

Verification IP is becoming much more than a bus-functional-model (BFM) or a passive checker designed to monitor a set of assertions at the interface. Commercial verification IP offer pre-defined compliance tests, inject errors, and drive directed-random traffic through the interface for system-level verification.

While the market is quickly defining requirements for commercial verification IP, there are several other requirements already evident. Commercial solutions must be flexible, enabling designers to easily configure a model that represents another vendor's chip interface. This enables design teams to share representations of the interface with other designers to verify chip-to-chip interoperability.

This brings up the need for a highly portable solution. Verification IP must integrate easily into the widely varying simulator and testbench environments that exist even within the same company. Other requirements include easy integration to coverage and debug tools and transaction recording. Full verification of the interface also requires an integrated solution for driving traffic, injecting errors and running complete compliance suites.

Successful verification IP products must address coverage, traffic generation, compliance suites, and must be configurable to model vendor-specific devices. Successful verification IP companies will combine EDA expertise with an expert level understanding of interface standards to provide an integrated product compatible with all verification tools and languages.

Functional verification is a looming challenge for chip designers. Standard interfaces are a natural target for dramatic improvements in verification productivity. And, the EDA industry is responding. The availability of commercial verification IP for standard interfaces is now enabling chip designers to slash a significant percentage of the overall verification cost, and offers an effective mechanism for ensuring chip-to-chip interoperability.

The next big leap in functional verification? Divide and conquer, starting with verification IP for complex chip interfaces.

Kevin Silver is vice president of marketing at verification IP provider Denali Software.