New DINI Two Chip Altera Stratix V Board for High-Speed, Low-Cost, ASIC Prototyping
October 14, 2013 -- The DINI Group announces the availability of a new Altera Stratix V FPGA board with a capacity of 16.5 million ASIC gates. The DNS5GX_F2 joins a long list of FPGA-based ASIC prototyping products from the industry’s established leader in large FPGA platforms.
The DNS5GX_F2 employs the high I/O-count, 1932-pin, flip-chip BGA package. Abundant interconnects are provided between the FPGAs, easing any difficult partitioning task. The largest Stratix V device, the 5SGXAB has a total of 840 I/Os along with 48, 14.1-Gbps transceivers. All are enabled. FPGA to FPGA busses are routed and tested as unidirectional source synchronous LVDS to run at 700MHz+ (1.4 Gb/s with DDR). Two DDR3 SODIMMS provide massive on board memory. Two expansion connectors allow for flexible customization.
To maximize flexibility, DINI Group introduces a flexible daughter card called IOB. An IOB card hosts 24, 14.1 Gb/s transceivers. Each FPGA has two IOB positions for a total of 4 on the DNS5GX_F2. Off-the-shelf IOB cards include 100 GbE Ethernet (via a CFP module), 40 GbE Ethernet, Quad QSFP+, Octal SFP+, GEN1/GEN2 PCIe, USB3.0 or SMAs.
“We made this new Stratix V board as versatile as possible.” says Mike Dini, president, “There is a Marvell ARM Processor, running Linux, for any custom interfaces you might need and plenty of power and cooling for high speed logic emulation. Prototyping networking logic is very easy with the multitude of flexible high speed interfaces. Software and firmware developers will appreciate the productivity gains that come with this low cost, stand-alone development platform.” DINI Group is an established leader in large, FPGA-based boards, critical IP, and systems. DINI Group FPGA boards are used in large quantities for ASIC and SOC prototyping, low-latency trading, and high performance computing. From their corporate campus in La Jolla, California, DINI Group employees have supplied over twelve billion ASIC gates.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Algo-Logic Systems Launches Industry-First 40Gbps TCP Endpoint on Altera Stratix V for Datacenter Acceleration
- Altera Unveils 28-nm Stratix V FPGA Family
- Altera's Stratix V FPGAs Provide RLDRAM 3 Memory Support
- Altera's 28-nm Stratix V FPGA Selected by Infinera For Use in DTN-X Multi-Terabit Packet-Optical Transport Network Platform
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers