DAC panel spotlights rise of IP subsystems
Dylan McGrath, EETimes
6/7/2012 1:41 AM EDT
SAN FRANCISCO—Intellectual property (IP) reuse in SoC design is increasing, creating challenges in compatibility and complexity, according to executives on a Design Automation Conference (DAC) panel. To minimize this complexity, panelists said, the semiconductor industry will increasingly turn to IP subsystems—larger chunks of IP that have been stitched together from many smaller blocks and pre-verified to ensure performance.
Naveed Sherwani, president and CEO of chip design and manufacturing services provider Open-Silicon Inc., said he was happy to see that IP reuse was finally occurring on a large scale, but said the trend is creating challenges.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- M31 Unveils Full Range of Automotive IP Solutions at ICCAD Illuminating the Future of Automotive Chip Development
- QuickLogic Announces Appointment of Andy Jaros as Vice President of IP Sales
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- BrisbaneSilicon publishes Beta Release of its Lumorphix Processor IP Core
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack