Customers using ASICs move to 32-bit MCUs

By Ata Khan
Jul 7 2005 (10:43 AM)

Many customers that have primarily used ASIC design in the past have recently begun to move toward using and evaluating microcontroller (MCU)-based systems. This is an increasing trend that seems to be based upon several factors:

1. Risk reduction via simplification of design

Risk is expensive. Pulling a large ASIC together requires integrating a processor subsystem, peripherals, a high-speed bus fabric, memory interfaces and the customer's proprietary logic. It lowers time-to-market by reducing design task implementation of proprietary logic and communication with the MCU instead of designing the entire system, including verification, timing closure, testability and manufacturability " thus reducing the risks involved.

Verification of the design before integration of the ASIC is problematic because it requires designs to preserve real-time behavior. Regardless of whether hardware prototyping systems or simulations are used, it is virtually impossible to replicate real-time silicon ASIC performance behavior in a prototyping environment. System responses will particularly differ from actual silicon behavior in a system with external interrupts and high-speed communication links such as high-speed USB, PCI Express, etc.

Different caches and memory latencies in one system can be constraints in a real-time performance. This situation becomes more difficult if real-time streaming data and quality of service issues are taken into account. It is certainly possible to ensure functional correctness and even cycle accuracy to a great degree, but real-time events do not normally scale uniformly in simulations. This can lead to the wrong bottlenecks and system constraints being highlighted in the verification method.

We were able to experience this when we produced a "system-chip." It included an ARM CPU, all the peripherals we could integrate on it, and the internal bus brought out in the pins. The idea was to couple this with FPGAs to attempt to simulate a system ASIC. However, the act of bringing out the internal bus to try to create a multi-chip ASIC impacted performance to a highly visible degree and did little to mitigate the overall risk.

On the other hand, using an available high-performance 32-bit processor coupled with external programmable logic allows the system to be prototyped in vivo and ensures that what is developed ends up being the final product.

2. Economies of scale

When use of a standard product is possible, the customer can benefit from the economies of scale produced by selling the same product in much higher volumes over the limitation of specific ASIC products.

There are not many programs that can deliver economies of scale in the first place, and even those that exist are subject to frequent redesigns to enhance performance, reduce costs, add features, etc. With a processor-based approach, the onus of maintaining cutting-edge performance and cost-efficiency is generally amortized over a much larger customer base and is also shifted from the customer to the supplier, who is motivated by both his customers and his competition to stay at the cutting-edge.

3. Mask costs for deep sub-micron (DSM) processes

A 90nm mask set is frequently cited as costing near $1 million. The increased risk here is, in addition to the first mask set cost, one or more additional spins are necessary since products at this level of complexity are very large and difficult to simulate totally. This risk is reduced considerably with an approach based on standard products.

4. Large number of gate equivalents

With a product containing millions of gate equivalents, it is highly likely that a bug fix will be required even though major first-time functionality and sampling should be achievable.

5. Embedded non-volatile memory (NVM)

There are many applications where the code size is small enough to fit into one megabyte or less of on-chip NVM, which brings many advantages to the customer such as security, lower power, higher speed and the increased ability to upgrade. Historically, ASIC and non-volatile process flows have not been combined, particularly in state-of-the-art process geometries.

Factors influencing this trend are the growth of 32-bit MCUs in the marketplace with more embedded designs and the introduction of increasingly high-performance MCUs and processors in the range of 250 MIPS and higher.

Processors in this class generally have high-speed memory and peripheral interfaces with industrial-strength operating systems such as Linux, Windows CE, etc. ported to them. We will see this trend intensify in the future when higher-performance processors are launched with programmable logic, allowing very quick implementations of large system designs and the option of optimization later if volumes and product lifecycles so dictate.

Shifts in processor use is shown in the following chart.

Ata Khan is the director of product innovation, Microcontroller Product Line, Philips Semiconductors