Creonic Announces FMC Board with L-Band RF Input for Satellite Applications
Kaiserslautern, Germany, Jan. 09, 2017 – Creonic GmbH, the market leader in satellite communication IP cores, today announced the availability of its FMC board with L-band RF input for Q2/2017. The card allows for building satellite receivers with throughputs of up to 800 Mbit/s. It complements Creonic’s proven portfolio of IP cores covering a wide range of standards for satellite communication such as DVB-S2X, DVB-RCS2 or CCSDS.

FPGA Mezzanine Cards (FMC) are daughter cards that can be plugged into existing FPGA carrier boards with FMC connector. The Creonic FMC board is compliant with the VITA 57.1 FMC standard. It can be used with high pin count (HPC) as well as low pin count (LPC) connectors. The board is compatible with any FPGA FMC carrier board that can work with 1.8V low power IOs.
The receiver board includes an L-band tuner chip that can choose from an arbitrary center frequency within the L-band (925 – 2,250 MHz). The baseband bandwidth is programmable from 40 to 100 MHz. The used dual-channel 12-bit ADC allows for sampling rates of up to 250 MHz of I/Q data. It is possible to control LNBs with the integrated DiSEqC block. The board offers flexible clocking capabilities.
The PCB comes with an FPGA reference design for Xilinx FPGAs in VHDL, C++ software firmware as well as comprehensive documentation.
For more information, please visit the product page or contact us.
About Creonic
Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The company offers the richest product portfolio in this field, covering standards like DVB-S2X, LTE-A, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit our website at www.creonic.com.
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
- UA Link DL IP core
Related News
- Renesas Develops Bluetooth Low Energy RF Transceiver Technologies that Simplify Board Design, Reduce Circuit Size and Increase Power Efficiency
- Creonic Releases DVB-S2X Demodulator Version 6.0 with Increased Bitwidth and Annex M Support
- Creonic Updates Doppler Channel IP Core with Extended Frequency Band and Sampling Range
- Key Asic Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner
Latest News
- GUC Monthly Sales Report – November 2025
- Global Semiconductor Sales Increase 4.7% Month-to-Month in October
- CXL Adds Port Bundling to Quench AI Thirst
- Tenstorrent and AutoCore Announce Strategic Partnership to Power High-Performance RISC-V Automotive Computing with AutoCore.OS
- Tenstorrent Announces Availability of TT-Ascalon™