CEVA-TeakLite-II Boosts Performance and Functionality of CEVA's Most Deployed DSP Core

Leveraging on the success of CEVA-TeakLite, CEVA-TeakLite-II combines enhanced performance, functionality and speed with backward software compatibility

SAN JOSE, Calif. - January 10, 2004 - CEVA, Inc. (NASDAQ: CEVA; LSE: CVA), the leading licensor of digital signal processors (DSP) cores and communications solutions to the semiconductor industry, today launched CEVA-TeakLite-II - a high performance DSP Core delivering outstanding cost and power advantages required for today's consumer and wireless devices. CEVA-TeakLite-II delivers a fully synthesizable soft core and a process-independent design that allows licensees to specify the silicon area, power consumption and speed that best suits their needs.

CEVA-TeakLite-II, a single Multiply-Accumulate (MAC) 16-bit fixed point DSP core, achieves a 30% increase in performance compared to its predecessor core, reaching 200 MHz @ TSMC 0.13u G (worst-case conditions and process), for a fully synthesizable core. Combining superior code compactness and small silicon die size (0.4 mm2 for the DSP engine designed with TSMC 0.13u G process rules), CEVA-TeakLite-II is positioned to meet the needs of advanced applications such as 2G/2.5G Wireless Handsets, Portable Media Players, next generation Hard Disks and Optical Drivers, and Digital Cordless Phones.

CEVA-TeakLite-II builds on the architecture of CEVA-TeakLite and CEVA-Oak, the most established and successful DSP cores to date in CEVA's IP portfolio. CEVA-TeakLite and CEVA-Oak cores have been licensed to 50 partners worldwide who, since inception, have shipped an estimated 500M units of CEVA powered silicon. TeakLite-II is fully compatible to both CEVA-TeakLite and CEVA-Oak DSPs at assembly and binary levels, allowing its users to leverage both existing applications and the large software installed base already available.

"With over 500 million units shipped to date, there is no question as to the success of TeakLite powered solutions" said Gideon Wertheizer, EVP of CEVA. "CEVA-TeakLite-II enhanced feature set and performance offers our existing customers and future licensees the performance demanded of new applications while maintaining legacy software and the cost effectiveness of the TeakLite architecture."

With next generation wireless and digital media devices requiring larger program size, increased local frame buffers and efficient multi-tasking, CEVA-TeakLite-II further expands its predecessor's memory addressable space by offering up to 2 mega-byte address space for code memory and up to 2 mega-byte address space for data memory. The core significantly reduces system-on-chip development effort and cost through the integration of real time emulation and code trace modules, shortening both design and verification cycles. These debug features can be further used for field upgrades and updates. The core is complemented with a fully automated reference design implementation along with a verification & simulation environments - reducing both development cost and time-to-market.

CEVA-TeakLite-II is further complemented by extensive algorithms and applications from CEVA and the CEVAnet™ third-party development community.

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