CEVA Shatters Performance Record for Licensable DSP Core With CEVA-X
CEVA-X1620™ Exceeds 550 MHz to Enable High Performance Video, Imaging and Telecom Applications
SAN JOSE, Calif. - November 15, 2004 - CEVA, Inc. (NASDAQ: CEVA; LSE: CVA), the leading licensor of digital signal processors (DSP) cores and communications solutions to the semiconductor industry, today announced the CEVA-X1620 DSP core in silicon running at 550MHz (TSMC 0.13um). Surpassing 550 MHz opens up a world of new market possibilities for DSP-based multimedia and communication solutions including high-performance video, voice, imaging and networking applications, and further establishes CEVA-X1620 as the fastest and most innovative licensable DSP core in the industry.
The CEVA-X1620 is complemented by a Development Platform and Software Development Kit (SDK). The Development Platform incorporates all standard audio/video interfaces (5.1 channel audio, analog and digital video), LCD screen, CMOS sensor module, FPGAs for customers' system prototyping, Flash and MMC slots, and an ARM core module expansion slot. The CEVA-X1620 SDK includes a highly-optimized C compiler, three types of simulators and an advanced debugger, all included in an Integrated Development Environment (IDE). All components of CEVA-X tools are developed in-house by CEVA ensuring optimal performance.
"We are thrilled with the results of CEVA-X in silicon and the customer benefits of combining performance and power efficiency needed for today's modern DSP solutions," said Gideon Wertheizer, EVP of CEVA. "With unsurpassed performance in a DSP, CEVA-X is positioned to power an array of new markets such as portable and high-end home entertainment, wireless communications and broadband networking."
The CEVA-X DSP architecture offers best-in-class performance, scalability, and the lowest cost-of-development. The CEVA-X core is fully synthesizable allowing customers to port the design to any available commercial cell library and to manufacture at any foundry. No manual or specialized electronic circuit design is required - significantly shortening the design cycle and reducing the associated risk of silicon re-spins. CEVA-X1620, the first implementation of the CEVA-X architecture family, is a 16-bit data width, dual MAC DSP with four 40-bit arithmetic units. CEVA-X1620 also integrates level one data and program memory controllers, AHB-Lite interfaces and an On-Chip Emulation Module (OCEM) including a JTAG port.
About CEVA-X1620
CEVA-X is a scalable VLIW-SIMD DSP architecture delivering breakthrough performance at low power consumption. Uniquely, the CEVA-X is designed as a multipurpose architecture allowing it be deployed efficiently in a broad range of market solutions including 2.5G/3G multimedia phones, PDAs, digital cameras and camcorders, DTV and HD-DVD. CEVA-X enables licensees to efficiently develop software using high-level languages such C and C++ allowing re-usability and fast time to market.
About CEVA, Inc.
For more information about CEVA, Inc, visit the about section of our website.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- CAN-FD Controller
Related News
- Flex Logix and CEVA Announce First Working Silicon of a DSP with Embedded FPGA to Allow a Flexible/Changeable ISA
- Novatek Adopts CEVA's Latest Sensor Hub DSP for New Multi-sensor IP Camera SoC
- CEVA Announces its Most Powerful and Efficient DSP Architecture to Date, Addressing the Massive Compute Requirements of 5G-Advanced and Beyond
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
Latest News
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP