Celoxica Gives European Debut for MeP Development Kit Including Toshiba's Second Generation Audio VLIW CoProcessor
-Celoxica (LSE:CXA) today announced the latest release of its development kit for Toshiba's Media embedded Processor (MeP). The kit, with Toshiba's second generation MeP based audio VLIW Coprocessor (AVC2), provides programmable hardware and Celoxica's ESL design software that enables designers to develop digital audio processing applications that utilize the AVC2's new instructions and customized operations.
The kit enables designers to deploy Celoxica's DK Design Suite to prototype and validate MeP based designs that include the AVC2. By using the DK Design Suite designers can easily implement the AVC2 and custom design additional coprocessors directly from software algorithms. Pre-built libraries supplied with the kit provide access to the MeP custom instructions as well as extensive hardware peripherals such as dual gigabit Ethernet, dual DVI and dual S-Video. Celoxica's co-simulation manager simplifies HW/ SW verification and connects into Instruction Set Simulators. Over 50 design examples are shipped with the kit.
Masataka Matsui, Senior Manager, Digital Media SoC Dept., SoC Research & Development Center, Toshiba's Semiconductor company said, "By making AVC2 technology available through the Celoxica's MeP Development Kit, designers can quickly see the benefits that the AVC2 can bring to their MeP based SoC designs."
"This MeP Development Kit builds on previous collaborations with Toshiba and makes it even easier for designers to access the very latest high performance multimedia technology," said Sandeep Ram, vice president of EMEA sales for Celoxica. "Wrapping our C-based ESL design tools and hardware into the kit provides a low-risk, high-productivity route to design exploration for digital media SoC."
About Celoxica
A leader in electronic system level design (ESL), Celoxica is enabling the next generation of advanced electronic products by producing tools, boards, IP and services that turn software into silicon. Celoxica technology raises design abstraction to the algorithm level, accelerating productivity and lowering risk and costs by generating semiconductor hardware directly from C-based software descriptions. Adding to a growing installed base, Celoxica provides the world's most widely used C-based behavioral design and synthesis solutions to companies developing semiconductor products in markets such as consumer electronics, defense and aerospace, automotive, industrial and security. Celoxica is a publicly traded company on the Alternative Investment Market of the London Stock Exchange under the symbol CXA. For more information, visit: www.celoxica.com
About MeP
MeP is Toshiba's proprietary configurable processor that allows designers to customize processor configurations, including custom instructions and embedded memory capacity, in about 1 million different combinations. The processor features small chip size, low power consumption and high-speed processing. It is based on a 32-bit RISC processor, appropriate for digital media products that require processing of large volume of image and audio data, such as digital TVs and DVD recorders.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Ultra Ethernet Verification IP
Related News
- Celoxica Unveils ESL Design Kit for SOPC-Based Coprocessor Acceleration
- CSEM joins forces with GLOBALFOUNDRIES to deliver best-in-class Bluetooth Dual-Mode silicon IP for next generation portable audio
- Syntiant Introduces Second Generation NDP120 Deep Learning Processor for Audio and Sensor Apps
- Ateme and Fraunhofer Join Forces to Deliver Next Generation Audio
Latest News
- SiPearl Tapes Out Rhea1 Processor, Closes Series A, Preps Series B
- Thalia Design Automation launches AMALIA Platform 25.2
- Siemens’ Veloce CS selected by Arm for Neoverse Compute Subsystems verification and validation
- InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration
- ESD Alliance Reports Electronic System Design Industry Posts $5.1 Billion in Revenue in Q1 2025