Brite Semiconductor provides xSPI/Hyperbus™/Xcella™ controller and PHY total solution
Shanghai, China — Aug.5, 2022 — Brite Semiconductor (“Brite”), a leading custom ASIC & IP provider, today announced providing xSPI/HyperbusTM/XcellaTM memory (Flash, PSRAM, MRAM…) controller and PHY solution for custom SoC. This solution is verified using memories from memory manufactures such as GigaDevice, APMemory, Cypress (Infineon), Micron, Macronix etc., which can support customers to develop better products faster in different fields.
The eXpanded Serial Peripheral Interface (xSPI) JESD251 standard, ratified by JEDEC in July 2018, defines a high-data throughput, serial interface for memory. It provides high data throughput, low pin count and is primarily for use in computing, automotive, Internet of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400MT/s raw data throughput. It is mainly for nonvolatile memory devices for example NOR flash, NAND flash, a large number of memory vendors adopt it for PSRAM (Pseudo SRAM) or MRAM (Magnetic RAM). It is extensible for a higher data rate based on either a high data rate per bit or a wider data path,achieving 800MT/s.
Brite Semiconductor now can provide a total solution of xSPI controller and PHY for the advanced memory and also legacy Octal SPI, QSPI and SPI device. We adopt auto-flow-control technology to minimize the FIFO/SRAM utilization. Also another innovative feedback-sampling technology is used to increase the data rate which doesn’t have a DS, achieving maximum 400MT/s in 8D mode without DS. The solution has the following features:
- Support Flash, PSRAM and MRAM using SPI protocol
- Support Single/Dual/Quad/Octal SDR/DTR(DDR) SPI
- Support xSPI/HyperbusTM/XcellaTM specification
- Support xSPI profile1 and profile2 (HyperbusTM)
- Support XIP (eXecute-In-Place) for fast boot
- Support AXI burst type INCR/WRAP and Fixed (single beat)
- Support AXI data width 32/64/128… bit
- Support AXI strobe width 4/8/16... bit
- Support AXI maximum burst length 256
- Support AXI outstanding command, configurable outstanding capability
- Support maximum 4 CSn
- Support 3 Bytes or 4 Bytes address
- Support single-ended or differential clock
- Support with/without DS, no performance degradation without DS
- Three clock domains: APB, AXI, xSPI clock
- xSPI clock maximum frequency 200Mhz
- Full digital PHY, 1x clock, small area, over-sampling is unnecessary
- Maximum data rate 400MT/s (DDR, DTR) or 200MT/s (SDR)
- Support arbitrary command through APB register interface (READ SFDP, ERASE etc.)
- Programmable READ/WRITE command code
- Support 2x dummy cycles (extensible dummy cycles)
Note: HyperbusTM is a trademark of Cypress(Infineon), XcellaTM is a trademark of Micron.
"There is a greater demand of high throughput and low pin count for Industrial IoT, Automotive and Edge AI applications, the emergence of xSPI memory can meet such requirement,” said Yadong Liu, VP of Engineering at Brite Semiconductor. “In addition, Brite Semiconductor expands the DDR technologies to xSPI, adopting auto-flow-control and feedback-sampling technologies to achieve low area and high data rate, then provides the total solution of xSPI memory controller for the custom SoC."
About Brite Semiconductor
Brite Semiconductor is a leading custom ASIC and IP provider, and committed to provide flexible one-stop services from architecture design to chip delivery with high value and differentiated solutions.
Brite Semiconductor provides comprehensive silicon proven “YOU” IP portfolio and YouSiP (Silicon-Platform) solution, which can be widely adopted in 5G, AI, high performance computing, cloud and edge computing, network, IoT, industrial Internet and consumer electronics, etc. YouSiP solution provides a prototype design reference for system house and fabless to speed up the time-to-market.
Founded in 2008, Brite Semiconductor is headquartered in Shanghai, China with 5 design and R&D centers as well as 4 sales offices in China and the United States.
For more information, please visit www.britesemi.com
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- GOWIN Semiconductor USB 2.0 PHY Interface and Device Controller IPs Achieve USB-IF Certification
- eDisplay Port / Display Port v1.4 Tx PHY and Controller IP in 40ULP and 12FFC process nodes for lagless and pure UHD Displays is available for immediate licensing
- PCIe 5.0 SerDes PHY and Controller IP Cores for all High-End Serial connect Interfaces in advanced SoCs is available for immediate licensing
- HDMI 2.0 Tx PHY in 12FFC along with Controller IP Core with high lossless Audio/Video data transfer, licensed for a 4KTV SoC
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack