Avery Design Systems Scale-Out With NVMe over Fabrics Verification Solutions
TEWKSBURY, Mass.– August 9, 2016 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of NVM Express over Fabrics 1.0 and NVM Express 1.2.1 extensions to its NVM-Xactor verification IP enabling verification of both NVMe over PCIe and NVMe over Fabrics designs.
NVM-Xactor is a complete verification solution for NVMe core and subsystem design. NVM-Xactor allows design and verification engineers to quickly and extensively test the functionality of NVMe controller designs targeting memory or message transports. The NVM-Xactor solution includes:
- NVM host software BFM
- NVM host and controller bus/fabric adaptor
- Reference NVMe controller and adaptor
- Producer-consumer scoreboard
- Compliance testsuite
- Comprehensive protocol checks
- Protocol analyzer tracker
- Functional coverage model
- Works with any PCIe and AXI IP or VIP
- Developed in native SystemVerilog UVM
“NVMe over Fabrics is an essential technology to scale-out NVMe storage connectivity using the simplicity and efficiency of an End-to-End NVMe model”, said Chris Browy, VP Sales and Marketing of Avery Design Systems. “Our industry leading NVM-Xactor now spans the spectrum of client to enterprise NVMe design applications”.
“CNEX Labs has effectively employed the Avery NVMe and PCIe VIP for the development of our semiconductor solutions. Using these models and compliance testsuites has helped us to achieve comprehensive, high quality verification for our ASIC designs”, said Justin Heindel, VP Product for CNEX. “The technical support has been excellent, and we look forward to using Avery VIP products on future NVMe designs.”
NVM-Xactor works in conjunction with various physical transport layers including Avery’s leading PCI-Xactor PCI Express and AMBA Verification IP solutions or other fabric interfaces such as Ethernet, Fibre Channel, or Infiniband to supply a complete NVMe subsystem verification environment. A NVM bus/fabric adaptor layer provides memory and RDMA transport access interface by the NVM host software BFM to the NVMe Controller via the full bus/fabric protocol or through a bypass mode yielding faster simulation performance for large data movement. A reference NVMe controller layer also supports core-level verification by emulating the NAND Flash backend subsystem.
Visit us at the Flash Memory Summit August 9-11 in booth #836.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI CSI, DSI, Soundwire, and Unipro, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SATA Express, eMMC, SD/SDIO, CAN FD, and I2C standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
- Avery Design Systems Announces NVMe 1.3 and NVMe-MI Verification IP Updates
- Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs
- Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications