Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way?
RISC-V’s advantages—customizability, scalability, and cost-effectiveness—make it a strong competitor to Arm.
By Emily Newton, EETimes Europe (December 24, 2024)
Could the fifth generation of reduced instruction set computing (RISC) dethrone the long-established advanced RISC machine (Arm) and x86 architectures? While the discussion about Arm versus RISC-V is hotly debated, the benefits of this open standard cannot be overlooked. How soon could it achieve market dominance?
RISC-V is poised to reshape the chip landscape
RISC-V is rapidly gaining momentum. If current trends continue, it may surpass long-standing proprietary architectures like x86 and Arm. Some trendsetters have already embraced the latest instruction set architecture (ISA).
For instance, Nvidia’s existing graphics processing units are managed by up to 40 custom RISC-V cores developed in-house, depending on complexity. The company began transitioning away from proprietary microcontrollers in 2015, just five years after the open-standard ISA was introduced. Industry giants such as Google, Qualcomm, and Samsung have made similar moves.
For decades, proprietary ISAs have arguably stifled R&D progress. One of RISC-V’s advantages is that it facilitates collaborative solutions and encourages cost-effective experimentation, which in turn fosters innovation. Organizations no longer have to be held back by proprietary chip designers’ slow-moving product roadmaps.
A change like this would have enormous implications for global chip fabrication capacity and supply. For instance, according to the European Strategy and Policy Analysis System, it could propel the EU’s share of global chip revenue, which dropped from about 20% in the 1990s to less than 10% in the 2020s.
Why is RISC-V gaining significant momentum?
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- What’s on tap from RISC-V in 2025?
- Third day for Arm vs Qualcomm trial
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- SpacemiT Secures Hundreds of Millions in A+ Financing to Accelerate RISC-V AI CPU Product Iteration
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack