Arm Responds to RISC-V, and More
By Kevin Krewell, EETimes
October 11, 2019
Arm CEO Simon Segars announced the changes in his opening keynote at Arm TechCon. After decades of tight control over the Arm instruction set architecture (ISA), Arm has finally decided that it can allow its licensees to build their own custom instructions, which are often useful to accelerate specialized workloads.
To read the full article, click here
Related Semiconductor IP
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
Related News
- IAR platform boosts embedded development with upgraded toolchains for Arm and RISC-V
- Arm vs. RISC-V: Same DNA, Different Flight Paths
- M5ERS Joins Arm Flexible Access Program to Accelerate Development of Ultra-Low-Power APU Products
- MIPS S8200 Delivers Software-First RISC-V NPU To Enable Physical AI at the Autonomous Edge
Latest News
- Rebellions Collaborates with SK Telecom and Arm Targeting Sovereign AI and Telecom Infrastructure
- Sarcina Launches UCIe-A/S Packaging IP to Accelerate Chiplet Architectures
- BrainChip Unveils Radar Reference Platform to Bridge the ‘Identification Gap’ in Edge AI
- Siemens accelerates AI chip verification to trillion‑cycle scale with NVIDIA technology
- SiFive Raises $400 Million to Accelerate High-Performance RISC-V Data Center Solutions; Company Valuation Now Stands at $3.65 Billion