ARC populates 600, 700 roadmaps with exemplar cores

Peter Clarke
(02/10/2005 6:24 AM EST)

  LONDON — ARC International plc (Elstree, England), a licensor of configurable processor cores, has prepared a road-map of illustrative examples in its ARC 600 and ARC 700 family lines.

The main difference between the ARC 600 and the ARC 700 is that the ARC 600 has a five-stage pipelined arithmetic logic unit achieving 1.3 dhrystone MIPS per megahertz while the ARC 700 has a seven-stage pipeline and achieves 1.2 dhrystone MIPS per megahertz but which can be pushed to higher clock frequencies, typically 400-MHz in a 0.13-micron manufacturing process.

The two families now include a number of preconfigured but still configurable cores that offer pre-optimized size, speed and power characteristics to meet specific requirements of various embedded markets, according to ARC. Each core in the 600 and 700 families consumes significantly less silicon area and power when compared to fixed processors from competing companies, and extends ARC's processor architecture to a wider range of consumer, storage and networking applications.

The ARC 600 family now includes the 605, the 610D with or without the ARC XY DSP coprocessor and the ARC 625D with or without the ARC XY. The ARC 700 family includes the 710D, 725D and 750D each of which can be deployed with or without the ARC XY DSP extensions.