Amidst export restrictions, RISC-V continues to advance
By Abhishek Jadhav, embedded.com ( November 29, 2023)
The RISC-V architecture continues to advance despite uncertainties over geopolitical tensions.
In the ever-changing semiconductor and computing technology environment, the RISC-V instruction set architecture (ISA) stands out as having potential to transform some aspects of industry. However, current geopolitical events make for uncertainties that present challenges for the open-source technology, especially with discussions around government export control restrictions on its development and implementation.
Unlike many proprietary ISAs, such as Arm, RISC-V is different in that it offers an open standard, freely available for anyone to develop and adopt. This open-source model has cultivated a dynamic global community of engineers and researchers leading a wave of innovation around RISC-V.
RISC-V is expected to follow the same trajectory as Linux, which has expanded over time as a result of the open-source community’s contributions. This community is actively working on developing both ISA and non-ISA standards for RISC-V. By leveraging open-source development, RISC-V is helping accelerate innovation and potentially pave the way for novel technological breakthroughs.
To read the full article, click here
Related Semiconductor IP
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
Related News
- China's Semiconductor Industry to Brace for Impact as SMIC Assesses Export Restrictions Placed by U.S., Says TrendForce
- PQShield and SiFive collaborate to advance post-quantum cryptography in RISC-V
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack