Altera eyes FDSOI process for FPGAs
Peter Clarke, EETimes
12/15/2012 8:13 AM EST
LONDON – A senior engineer at FPGA vendor Altera has evaluated fully-depleted silicon on insulator (FDSOI) chip manufacturing process and concluded that the technology could have particular benefits for FPGAs. This raises the possibility that Altera could be considering replacing Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) as its foundry of choice or operating a multiple-foundry manufacturing strategy in the future.
Jeff Watt, an Altera fellow and technology development specialist, presented An evaluation and benchmarking of 14-nm fully-depleted technology for FPGAs at an evening symposium on FDSOI held alongside the International Electron Devices Meeting in San Francisco.
To read the full article, click here
Related Semiconductor IP
- SATA Host on Altera Arria II GX
- SATA Device Controller on Altera Arria II GX
- Aurora-like 8b/10b @3Gbps for ALTERA Devices
- Aurora-like 64b/66b @14Gbps for ALTERA Devices
- eCPRI Altera® FPGA IP
Related News
- Intel Launches Altera, Its New Standalone FPGA Company
- 30 minutes with Altera CEO Sandra Rivera discussing the Past, Present, and Future of a major FPGA vendor
- Altera Starts Production Shipments of Industry’s Highest Memory Bandwidth FPGA
- Altera Closes Silver Lake Investment to Become World’s Largest Pure-play FPGA Solutions Provider
Latest News
- IAR accelerates SDV development with Infineon DRIVECORE bundles and AURIX™ RISC-V Debug capabilities
- Ceva Launches PentaG-NTN™ 5G Advanced Modem IP, Enabling Satellite-Native Innovators to Rapidly Deploy Differentiated LEO User Terminals
- Faraday Broadens IP Offerings on UMC’s 14nm Process for Edge AI and Consumer Markets
- Accellera Approves Clock and Reset Domain Crossing (CDC/RDC) Standard 1.0 for Release
- Jmem Tek Joins the Intel Foundry Accelerator Ecosystem Alliance Program, Enabling JPUF and Post-Quantum Security Designs