Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0 2022-08-05 07:07:00 Verification IP
Efinix® Extends Breakthrough Family of Titanium Products with Launch of the Titanium Ti180 FPGA 2022-08-04 16:50:00 FPGA
Intel Orders Delayed, TSMC Slows Three-Nanometer Expansion, Says TrendForce 2022-08-04 16:50:00 Commentary / Analysis
Edge Impulse Releases Deployment Support for BrainChip Akida Neuromorphic IP 2022-08-04 16:50:00 Embedded Systems
June Swoon - IC Sales Turn Negative as Economy Weighs on Market 2022-08-04 16:50:00 Commentary / Analysis
Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products 2022-08-04 08:20:00 EDA
UCIe™ (Universal Chiplet Interconnect Express™) Consortium Announces Incorporation and New Board Members; Open for Membership 2022-08-03 12:06:00 Other
Alma Technologies Announces the Immediate Availability of an Ultra-High Throughput Image Scaler IP Core 2022-08-03 10:05:00 IP
Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library 2022-08-03 08:14:00 EDA
Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard 2022-08-03 08:08:00 Other
Global Semiconductor Sales Increase 13.3% in Q2 2022 Compared to Q2 2021 2022-08-03 05:34:00 Commentary / Analysis
CXL Consortium Releases Compute Express Link 3.0 Specification to Expand Fabric Capabilities and Management 2022-08-03 04:40:00 Other
Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development 2022-08-02 15:07:00 Business
Avery Announces 800G Ethernet VIP virtual network co-simulation platform, enabling SoC pre-silicon validation in real networked application environments 2022-08-02 14:00:00 Verification IP