0-In verification monitor checks HyperTransport protocol
0-In verification monitor checks HyperTransport protocol
By Michael Santarini, EE Times
November 27, 2001 (12:39 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011127S0029
SAN MATEO, Calif. Tool vendor 0-In Design Automation Inc. has released a version of its CheckerWare monitor for the HyperTransport I/O Link Protocol standard. 0-In said the HyperTransport monitor will help designers develop chips that use the protocol. Developed largely by Advanced Micro Devices Inc., HyperTransport technology provides a low-latency, low-pin-count, high-speed link between chips inside computers and communication devices, and is said to make interaction between devices up to 48 times faster than some existing bus technologies. The 0-In development team used AMD's simulation environment to ensure that its HyperTransport monitor complies with the latest version of the HyperTransport I/O Specification. The protocol monitor is essentially an executable specification for the HyperTransport standard, and therefore is likely more precise and accurate than t he written document itself, 0-In said. A customer has used the HyperTransport monitor successfully in a design, the company said. The monitor supports many modes and features of the HyperTransport Protocol, including End, Node and Bridge implementations, all CAD widths, error handling and low-level link initialization.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Parameterizable compact BCH codec
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
Related News
- Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
- Siemens introduces Questa Verification IP solution support for the new CXL 3.0 protocol
- HyperTransport licence for FPGAs
- HyperTransport Consortium adds eight member companies
Latest News
- Access Advance and Via Licensing Alliance Announce HEVC/VVC Program Acquisition
- Efficient Computer Launches Electron E1 Evaluation Kit to Accelerate Energy-Efficient Computing
- S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
- Qualitas Semiconductor Signs First ASIL-B-Compliant MIPI Sub-system IP Agreement for Autonomous ADAS SoC
- ISOLDE Project Demonstrates Advancements in European Open-Source RISC-V for Automotive, Space, and IoT