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wideband Analog Front End IP

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Search (7)
Compare 7 IP from 1 vendors (1 - 7)
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • Programmable Low Power SERDES on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
    • Compact form factor – 0.104 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.8 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN28HPL
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.095 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.6 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.107 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.9 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on Samsung 28LPP
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.134 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 7.0 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.165 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.5 mW/Gbps including termination
    • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
  • Custom Programmable Low Power SERDES on GLOBALFOUNDRIES 65G
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.172 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 11 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
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