umc/ IP
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UMC 55nm ULP Bandgap / Current Reference
- 3σ 4% untrimmed voltage reference accuracy.
- 1% variation over -40ºC to 125ºC after trimming.
- 70dB low frequency PSRR.
- Trimmed, temperature compensated, 10µA reference current outputs with 3% accuracy.
- Trimmed IPTAT output currents can be provided.
- Less than 8µV noise from 0.1Hz to 10KHz.
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On-Chip IO to Core Voltage Buck Regulator on UMC 55nm ULP
- The OT1153 series on-chip regulators allow for efficient on-chip conversion of IO voltages to Core voltages.
- E.g. 3.3V to 1.2V with only one external inductor and one external capacitor.
- 2MHz conversion frequency is used to minimize the size of the external components. Input voltages of 2.5-5V are available and currents up to 80mA.
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128x1 Bits OTP (One-Time Programmable) IP, UMC 0.18um 1.8V/5V BCD Process
- Fully compatible with UMC 0.18um 1.8V/5V BCD process
- Wide operating voltage range: 1.9-5.5V read voltage, 5.5V+/-5% program voltage
- High speed: 10µs program time per bit
- Wide temperature range: -40°C to 125°C for read and 25°C (i.e. room temp) for program
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256x1 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
- Fully compatible with UMC Logic/Mixed-Mode 110nm Aluminum Enhancement Shrinkable CMOS process
- Low program voltage: 3.8V±5% VDDP and 1.2V VDD
- Low read voltage: 1.08–1.32V VDD and VDDP
- High speed: 10µs program time per bit
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512x1 Bits OTP (One-Time Programmable) IP, UMC 0.18um 1.8V/5V BCD Process
- Fully compatible with UMC 0.18um 1.8V/5V BCD process
- Wide operating voltage range: 1.9-5.5V read voltage, 5.5V+/-5% program voltage
- High speed: 10µs program time per bit
- Wide temperature range: -40°C to 125°C for read and 25°C (i.e. room temp) for program
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4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
- Fully compatible with UMC Logic/Mixed-Mode 110nm Aluminum Enhancement CMOS process
- Low voltage: 1.2 V ± 10% read voltage, 3.8 V ± 5% program voltage
- High speed: 10-µs program time per bit
- Wide temperature: -40°C to 125°C read and 10°C to 40°C program
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Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
- DisplayPort version 1.4 compliant receiver
- PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
- Integrated 100-ohm termination resistors with common-mode biasing
- Integrated equalizer with tunable strength
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
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12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
- A universal SERDES IP that operation from 1Gbps to 12.5 Gbps
- Compatible with PCIe/USB3/SATA base Specification
- Support 40-bit/32-bit/20-bit/16-bit parallel interface
- Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps)