ultra-low memory IP
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Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
- Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
- With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
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Ultra-low power high dynamic range image sensor
- Resolution: VGA (640 x 480)
- Backside illuminated sensor
- Pixel size: 6.3 μm x 6.3 μm
- Fill factor: 83 %
- Dynamic range: 120 dB intra-scene
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In Memory Computing (IMC)
- CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data often has to be sent from an IoT device to a server for processing, which creates a connectivity requirement and an unavoidable latency.
- For time critical applications this is not acceptable and so there is a drive to do more computation within the device itself, i.e., AI processing at the Edge.
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Ultra-low voltage, SRAM
- SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus.
- Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
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OCTARAM Memory Model
- Supports OCTARAM memory devices from all leading vendors.
- Supports 100% of OCTARAM protocol standard specification.
- Supports all the OCTARAM commands as per the specification.
- Supports device density up to 256MB.
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ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
- Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
- Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
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Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit RISC-V embedded CPU with balanced 3-stage pipeline
- DSP implementation to extend the RISC-V baseline (RMX-100D)
- 2 KB to 64 KB instruction L1 cache
- Up to 2MB instruction and data closely coupled memory (CCM)