Transceiver IP

This SLVS I/O Library, implemented in TSMC 22nm with an 11P7M_5X1Z UT-AlRDL metal stack, provides a 0.9V differential transceiver optimized for low-power, high-speed operation.
Supporting data rates up to 200 Mbps and compliant with JESD8-13 SLVS standards, the library features strong power supply rejection, integrated 100 on-die termination, and robust 2 kV HBM / 500 V CDM ESD protection.

This library delivers a compact and reliable 1.2V SLVS transceiver solution in UMC 110nm, optimized for high-speed, low-power applications.
Featuring robust supply and ground noise rejection, 2kV HBM ESD protection, and integrated on die termination, this library provides both transmit and receive paths compliant with JESD8-13 SLVS standards at up to 200 Mbps.

Our FD-TRx Series is a transceiver comprising both of our breakthrough flagship FDDAC and FDADC technologies in a single chip offering a full solution for bi-directional connectivity.
Its ultra-wide coherent modulation bandwidth and low energy consumption make it ideally suited for wide bandwidth applications such as mmWave-WiFi, mmWave5G and 6G, radar, or satellite.

The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performance applications.
This tri-band system delivers exceptional wireless communication capabilities with support for Wi-Fi 6/6E/n/g/b/a, enabling seamless connectivity across a wide frequency spectrum (5.925–7.125 GHz).
With support for advanced 4096-QAM modulation, the IP is capable of ultra-high data throughput, making it an ideal solution for bandwidth-intensive applications requiring low latency, fast data rates, and robust connectivity.

The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.

The MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY specification version 1.1.
It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols at speeds up to 1.5Gbps per lane.
It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver.

The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.

This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity.
Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C).

This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process.
Designed with 1.8V thick oxide devices and a standard low-voltage core interface at 0.8V, this transceiver ensures robust operation across a wide temperature range (-40°C to 125°C).
Supporting high-speed differential signaling up to 2Gbps, it delivers ex- ceptional signal integrity with low jitter and precise eye diagrams.

The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.

transceiver IP