transceiver IP

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Compare 945 IP from 115 vendors (1 - 10)
  • Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
    • The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performance applications.
    • This tri-band system delivers exceptional wireless communication capabilities with support for Wi-Fi 6/6E/n/g/b/a, enabling seamless connectivity across a wide frequency spectrum (5.925–7.125 GHz).
    • With support for advanced 4096-QAM modulation, the IP is capable of ultra-high data throughput, making it an ideal solution for bandwidth-intensive applications requiring low latency, fast data rates, and robust connectivity.
  • MIPI M-PHY® 3.1 Analog Transceiver
    • The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
    • The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 3.1 Analog Transceiver
  • MIPI D-PHY Analog Transceiver IP Core
    • The MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY specification version 1.1.
    • It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols at speeds up to 1.5Gbps per lane.
    • It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver.
    Block Diagram -- MIPI D-PHY Analog Transceiver IP Core
  • MIPI M-PHY® 4.1 Analog Transceiver
    • The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 4.1 Analog Transceiver
  • LVDS Transceiver in TSMC 28nm
    • This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity.
    • Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C).
    Block Diagram -- LVDS Transceiver in TSMC 28nm
  • SLVS Transceiver in TSMC 28nm
    • This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process.
    • Designed with 1.8V thick oxide devices and a standard low-voltage core interface at 0.8V, this transceiver ensures robust operation across a wide temperature range (-40°C to 125°C).
    • Supporting high-speed differential signaling up to 2Gbps, it delivers ex- ceptional signal integrity with low jitter and precise eye diagrams.
    Block Diagram -- SLVS Transceiver in TSMC 28nm
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
    • AD_SLVS_LVDS is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is flexible enough for any system.
    • To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm.
    • This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.
    Block Diagram -- 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
  • USB3.1 transceiver IP with PMA and PCS layer
    • Data rate for Gen 1 physical layer is 5Gbps
    • Data rate for Gen 2 physical layer is 10Gbps
    • 4 Channel per Quad
    • Shared high performance LC tank PLL
    Block Diagram -- USB3.1 transceiver IP with PMA and PCS layer
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