multi-protocol SERDES IP
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IP
from 10 vendors
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250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- Layout for wirebond packaging
- Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
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125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- Removes the need to license multiple SERDES.
- Includes PCIe Gen 5 controller at no additional cost.
- Off the shelf solution, cost effective
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1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Multi-protocol ePHY IP supports 1-56/112Gbps data rates
- Low-Jitter Transmitter with 8-tap de-emphasis FIR
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16G Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
- Duplex lane configurations of x2, x4, and x38
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
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16G Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
- Duplex lane configurations of x2, x4, and x38
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
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32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
- Supports data rates of 2.5 to 32 Gbps
- Optimized for low-power operation and north/south die-edge placement
- AC-coupled RX front end with on-chip capacitors
- Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
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28G LR Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
- Optimized for low-power operation and north/south die-edge placement
- Duplex Lane configurations of x4 and x1
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28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
- Optimized for low-power operation and north/south die-edge placement
- Duplex Lane configurations of x4 and x1