eDisplay Port/Display Port v1.4 IP
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eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
- Low power operation: 22mW/lane @ typical
- Support data rate: 0.6Gbps~5.4Gbps
- Utilize 10bit parallel interface for per lane
- Independent power down control for each lane
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eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
- Support data rate of main link : 0.6Gbps~4.0Gbps
- Utilize per-lane 10/20bit parallel interface for main link
- Support Spread Spectrum clock generation: -
- 5000ppm@31.5KHz
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HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+
- Compliant with HDMI 1.4b & Display Port version 1.4 specification.
- Input clock 135MHz for Display Port.
- Supports upto HBRII (5.4Gbps/Ch) of DP 1.2 standard, 3D 1080p @60Hz.
- Up to 21.6Gbps BitRate (4 X 5.4Gbps/Channel) in DP mode, 10.2Gbps (3 X 3.4Gbps/Channel) in HDMI mode.