Xiphera IP

Balanced Between Speed and Resource Requirements: XIP8103B can achieve over 2 Gbps throughput, while consuming only about 4000 Lookup Tables (LUTs) in a typical FPGA implementation.
Versatility: XIP8103B supports the forward prediction resistance mode, which can be set on and off between output generation, as well as the use of personalization strings and additional inputs for instantiation and reseeding.
Standard Compliance: XIP8103B is compliant with the NIST SP800-90A specification.
XIP8103B can be combined with Xiphera’s NIST SP800-90Bcompliant XIP8001B to form a NIST SP800-90C compliant Random Bit Generator (RBG).

Versatility: IP3324B supports the widely used cryptographic hash function SHA-512. It also has native support for commonly used message authentication code (HMAC) based on SHA-512 and key derivation function (HKDF) based on HMAC. This allows using XIP3324B for multiple cryptographic functions —for example, TLS 1.3 —more easily and efficiently than an IP core that supports only SHA-512.
Constant Latency: The execution time of XIP3324B is independent of the message and key values (apart from message length), and consequently provides protection against timing-based side-channel attacks.
Performance: XIP3324B provides high performance and reaches hashing speeds of several hundreds of Mbps.
Compact Size: XIP3324B has compact size (for example, 2483 ALMs and, 6 M20K blocks in Intel ® Cyclone ® 10 GX family) permitting integration into resource constrained FPGA designs. Contact sales@xiphera.com for ASIC resource requirements.