AES-XTS, Advanced Encryption Standard (256-bit key), XTS mode IP Core

Overview

XIP1183B from Xiphera is a balanced Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) with 256 bits long key in XTS mode.

AES-XTS is block-oriented cipher used primarily for protecting the confidentiality of data at rest. Consequently, AES-XTS is widely used for encrypting the contents of hard drives and other storage devices.

AES-XTS is a tweakable block cipher, and as it instantiates the underlying AES block cipher twice, the key material for AES-XTS is twice longer than for the constituent individual AES block ciphers.

The encrypted data depends not only on the plaintext and encryption key, but also on the logical address of the data on the storage device. This means that identical plaintexts get encrypted differently at different logical addresses.

XIP1183B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1183B does not rely on any FPGA manufacturer-specific features.

XIP1183B has also been successfully validated in the CAVP (Cryptographic Algorithm Validation Program) by NIST (National Institute for Standards and Technology).

Key Features

Moderate resource requirements: The entire XIP1183B requires 6074 Adaptive Lookup Modules (ALMs) (Intel Cyclone ® 10 GX), and does not require any multipliers or DSPBlocks.
Performance: XIP1183B achieves an impressive throughput in the Gbps range, for example 3.20+ Gbps in Xilinx Kintex ® UltraScale+.
Standard Compliance: XIP1183B is compliant with both the Advanced Encryption Algorithm (AES) standard, and the XTS standard.
Optional Ciphertext stealing support as defined in IEEE Std 1619-2018.
Increased Performance can be achieved by paralle instantiations of XIP1183B.

Benefits

Fully digital design
Portable to any ASIC or FPGA technology
Fully standard compliant
Easy to integrate
Several bus interfaces available
IP core designed in-house at Xiphera
Technical support by the original designers and cryptographic experts
CAVP validated

Block Diagram

Applications

XIP1183B protects the confidentiality of the encrypted plaintext, and identical plaintext is encrypted into a different ciphertext at different memory addresses.
When using XIP1183B XIP1183B protects the confidentiality of the encrypted plaintext, and identical plaintext is encrypted into a different ciphertext at different memory addresses.
When using XIP1183B with storage media whose natural bit width is smaller than 128bits, it is recommended to integrate XIP1183B with a memory controller IP core to enable encrypting and decrypting 128-bits data units.
with storage media whose natural bit width is smaller than 128bits, it is recommended to integrate XIP1183B with a memory controller IP core to enable encrypting and decrypting 128-bits data units.

Deliverables

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP1183B can be shipped in a number of formats, including netlist, source code, or encrypted source code.
Additionally, synthesis scripts, a comprehensive testbench, and a detailed datasheet including an integration guide are included.

Technical Specifications

Foundry, Node

Any

Maturity

Hardware tested

Availability

Immediate

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