WLAN IP

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Compare 17 IP from 12 vendors (1 - 10)
  • SiGe BiCMOS WLAN Power Amplifier
    • Linear Gain around 26 dB
    • High PAE, High Linearity
    • Maximum Linear Output Power in the range of 24dBm
  • 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
    • 8,900 ASIC gates at 802.11a/g OFDM data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC, AES0CTR per NIST SP800-38C)
    Block Diagram -- 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
  • 802.11a Physical Layer Baseband
    • Fully IEEE 802.11a standard compliant
    • Support for all data rates 6-54 Mbit/s
    • Available as Verilog source code without vendor specific IP cores
    • Synthesis possible for Altera and Xilinx FPGAs without source code changes
  • SD Card / SDIO Card Combo Device IP
    • SD / SDIO Card Combo Device IP core is SD memory controller and a SDIO controller with an AHB interface.
    • Combining with the optional NAND Flash Controller IP, the SD/SDIO Combo Device IP provides an integrated SD memory Card solution for designs that utilize NAND flash memory.
    Block Diagram -- SD Card / SDIO Card Combo Device IP
  • IEEE 802.11n/ac/ax Encoder and Decoder
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder
    • Layered decoding
    • Soft decision decoding
    • IEEE 802.11n/ac/ax standard compliant
    • Support all LDPC code rates (½, 2/3 , ¾, and 5/6 )
    • Support all LDPC codeword sizes(648, 1296, and 1944 bits)
  • Viterbi Decoder
    • Hard or soft decoder with configurable soft bit widths
    • Parameterisable generator polynomials
    • Parameterisable code Constraint length
    Block Diagram -- Viterbi Decoder
  • Digital Communications (incl 5G)
    • High processing power
    • Customizable hardware
    • Optimal algorithm mapping
    • User defined quantization
  • Bluetooth Dual Mode v4.2 RF Transceiver IP
    • TSMC40nm
    • High Volume Silicon Proven
    • Extracted from Design Data Base of production chip
    • Integrated balun
    Block Diagram -- Bluetooth Dual Mode v4.2 RF Transceiver IP
  • N-Point FFT/IFFT
    • Parameterisable FFT block size
    • Parameterisable input signal width
    • Parameterisable internal scaling type (unscaled, scaled on every stage, optimised scaling)
    • Programmable input and output word lengths and internal precision
    Block Diagram -- N-Point FFT/IFFT
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Semiconductor IP