802.11a Physical Layer Baseband
Overview
The 802.11a IP core allows to transmit and receive data packets according the IEEE 802.11a standard. CRC-32, digital up/down conversion, and RF control are included. The IP is available as Verilog source code.
Key Features
- Fully IEEE 802.11a standard compliant
- Support for all data rates 6-54 Mbit/s
- Available as Verilog source code without vendor specific IP cores
- Synthesis possible for Altera and Xilinx FPGAs without source code changes
- 80 MHz target frequency
- Runs on Virtex-4, Stratix II or faster devices
- Generic message interface for configuration, operation, and debugging
- Separate interfaces for control messages and data input/output
- RF control lines included (PA/TX/RX on/off, 16 parallel AGC lines, 3-wire serial bus)
- Generic AGC algorithm allows simple configuration via message interface
- Digital up and downconversion to/from 80 MS/s DAC/ADC interface for zero IF or 20 MHz low IF mode
- Message control via UART and internal data generator for PHY-only debugging directly from a PC
Benefits
- Possible applications include:
- 802.11a/p transmitter/receiver
- Proprietary communication systems
Deliverables
- Verilog source code
- Matlab/Octave control functions
- Documentation