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Vision Processor IP

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  • Image signal processor to advance vision systems for IoT and embedded markets
    • Multi-sensor interface with up to 20-bit linear video input
    • Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)
    Block Diagram -- Image signal processor to advance vision systems for IoT and embedded markets
  • ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Tensilica Vision P1 DSP
    • 256/128b Load/Store capabilities
    • 128 8-bit MAC
    • 8/16/32-bit fixed-point processing
    • Single-precision (FP32) and half-precision (FP16) floating-point processing
  • Tensilica Vision P6 DSP
    • 1024/512b Load/Store capabilities
    • 256 8-bit MAC
    • 8/16/32-bit fixed-point processing
    • Single-precision (FP32) and half-precision (FP16) floating-point processing
  • Tensilica Vision Q8 DSP
    • 2048/1024b Load/Store capabilities
    • 1024 8-bit MAC: 2X MAC capability versus Vision Q7 DSP
    • 8/16/32-bit fixed-point processing
    • Double-precision (FP64), single-precision (FP32), and half-precision (FP16) floating-point processing
  • 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
    • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
    • Symmetric multiprocessing up to 8 cores
    Block Diagram -- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
  • Low-power high-speed reconfigurable processor to accelerate AI everywhere.
    • Multi-Core Number: 4
    • Performance (INT8, 600MHz): 0.6TOPS
    • Achievable Clock Speed (MHz): 600 (28nm)
    • Synthesis Logic Gates (MGates): 2
    Block Diagram -- Low-power high-speed reconfigurable processor to accelerate AI everywhere.
  • NPU IP for AI Vision and AI Voice
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 3.0 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b
    Block Diagram -- NPU IP for AI Vision and AI Voice
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