Vision DSP IP
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16
IP
from 4 vendors
(1
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10)
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Imaging and Computer Vision Processor
- Superior performance
- Low power consumption
- Flexible and scalable
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Tensilica Vision P1 DSP
- 256/128b Load/Store capabilities
- 128 8-bit MAC
- 8/16/32-bit fixed-point processing
- Single-precision (FP32) and half-precision (FP16) floating-point processing
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Tensilica Vision Q7 DSP
- Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
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Tensilica Vision P6 DSP
- 1024/512b Load/Store capabilities
- 256 8-bit MAC
- 8/16/32-bit fixed-point processing
- Single-precision (FP32) and half-precision (FP16) floating-point processing
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Tensilica Vision Q8 DSP
- 2048/1024b Load/Store capabilities
- 1024 8-bit MAC: 2X MAC capability versus Vision Q7 DSP
- 8/16/32-bit fixed-point processing
- Double-precision (FP64), single-precision (FP32), and half-precision (FP16) floating-point processing
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Tensilica AI Max - NNA 110 Single Core
- Scalable Design to Adapt to Various AI Workloads
- Efficient in Mapping State-of-the-Art DL/AI Workloads
- End-to-End Software Toolchain for All Markets and Large Number of Frameworks
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Tensilica DSP IP supports efficient AI/ML processing
- Powerful DSP Instruction Set Supporting AI/ML Operations.
- Mixed Workloads.
- Industry-Leading Performance and Power Efficiency.
- End-to-End Software Toolchain for All Markets and a Large Number of Frameworks.
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High Performance Scalable Sensor Hub DSP Architecture
- Self contained, specialized sensor hub on-device processor
- Unifies multi-sensor processing with AI and sensor fusion
- Highy-configurable 8-way VLIW architecture
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Intelligent Vision Processor
- Fully programmable in high level languages
- Scalar and Vector units to handle a mix of control and parallel code efficiently
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General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
