Video Pipeline IP
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57
IP
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10)
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Pipelined AES G3 for Video
- Low area, pipelined implementation of AES with moderate key latency suitable for video encryption/decryption.
- Based on the NIST validated (Cert #953) AES-G3 implementation of the Advanced Encryption Standard 
- Supports 128, 192 and 256 bit keys
- Targets all modern FPGA families from Xilinx, Altera, Lattice and Microsemi
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RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing
- RTP/UDP/IP Protocol Hardware Stack, targets H.264 NAL Streams. See DB RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams
- For RX (i.e., receiving packets from the network), there is optional packet reordering to absorb network jitter.
- For both TX/RX, multiple NAL video streams supported. The DB-RTP-UDP-IP-NAL targets H.264 NAL Streams.
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4K Video Scaler IP Core
- Technology independent soft IP Core for FPGA, SoC and ASIC devices
- Supplied as human readable VHDL source code (or Verilog on request)
- Versatile RGB video scaler capable of scaling up or down by any factor
- Fully programmable scale parameters and scaler bypass function
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64 bit Video / Image DSP
- Custom Matrix instruction support
- Tightly-coupled vector unit
- 3-issue / Out-of-order / 8-stage scalar pipeline
- Full Linux OS support
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High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
- Design Flexibility
- Portability
- Ease of programmability
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Image Signal Processing Pipeline IP core
- Extremely flexible and versatile, ISPIDO can be tailored on ultra low powered battery operated devices, up to higher than 8K resolution vision systems.
- Each module of the image Signal Processing Pipeline, proposed by DPControl, has been implemented respecting the compatibility with the AMBA AXI4 standards, making the entire architecture completely configurable and versatile.
- The ISP accepts in input a video stream with 8 or 10 or 12 bits depth. The Defective Correction module takes care of eliminating the Salt-Pepper error.
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High Dynamic Range (HDR) Pipeline
- Digitally processes and enhances raw image data from HDR camera sensors
- Supports Xilinx® Zynq®-7000 AP SoC, 7 Series and newer
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UHD Image Signal Processing (ISP) Pipeline
- The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx ACAP, MPSoC, SoC and FPGA devices.
- It enables parallel processing of multiple Ultra HD video inputs in different programmable devices, ranging from the small Xilinx Artix®-7 FPGAs to the latest Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) devices.
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RTP/UDP/IP Protocol Hardware Stack – Raw, Uncompressed RGB/YUV Video Streams Packet Processing
- RTP/UDP/IP Protocol Hardware Stack with separate releases: 10/100/1000 MbE; 10/25 GbE
- Targets raw, uncompressed RGB/YUV video streams. See DB-RTP-UDP-IP-NAL for H.264 NAL Streams
- Internet Protocol (IP) Packet Processor: IPv4 and IPv6 (optional) & ICMP (Internet Control Message Protocol) Protocol; IP header checksum generator (transmitter) & check (receiver), userselectable Maximum Transmission Unit (MTU), Unicast, Broadcast &Multicast Packet support; Compliance with IETF IPv4/IPv6 RFCs
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Video Interlacer
- Supports any interlaced format
- 24-bit RGB or YCbCr video in/out
- Support for video resolutions of 4K and above
- Fully pipelined architecture with simple flow-control
