High performance dual-issue, out-of-order, 7-stage pipeline superscalar core

Overview

Key Features

• Dual-issue, out-of-order CPU architecture with a 7-stage pipeline.
• 32-bit RISC-V ISA, supporting RV32IMA(F)C sets, and partial P extension.
• 256-bit data bus and Load/Store architecture.
• Supports 16-bit, 32-bit fixed-point number operation, including integer and Q types.
• Optional single-issue/multi-issue micro-architecture, partial sequential issue and OOO execution.
• Equipped with instruction prefetch unit and dynamic branch prediction unit (BTB, BHT, RAS, JAL).
• Supports Physical Memory Protection (PMP).
• Supports Platform-Level Interrupt Controller (PLIC), 64 interrupts.
• Supports fast interruption and fast access to achieve more efficient real-time operation.
• Two privileges: Machine(M), User(U), and optional Supervisor(S) privilege.
• External AHB bus, 256-bit, RiVAI-R1 core can be either master or slave.
• Supports RISC-V debugging standard spec, supports JTAG.
• Flexible parameterized configuration:
• I-Cache/D-Cache space size
• ITCM/DTCM space size
• L2 SRAM size
• The number of interrupts
• Optional Floating-point unit (FPU)
• Optional Memory management unit (MMU)

Benefits

• Design Flexibility
• The RISC-V ISA offers a compelling level of flexibility, and RiVAI has capitalized on this with our product portfolio. The RiVAI-R1 CPU processor IP is able to build fit-for-purpose products that align with customer requirements and application workloads, with its easy arrangement of preemptive interrupts, size of I-Cache/D-Cache or ITCM/DTCM and L2 SRAM, and other optional modules like FPU, MMU…, thus, taking us further into the higher performance DSP market space.
• Portability
• One of the most unique and powerful capabilities of the RISC-V Vector Extension is that the ISA is vector-length agnostic. This means that code written for a RiVAI-V1 vector processor can run on any compatible RISC-V vector ISA processor, so it’s possible to experiment with different vector sizes to achieve the perfect balance of performance, power, and area for different application workloads, and projects are easily portable between processors and applications.
• Ease of programmability
• The RiVAI-R1 CPU processor’s new solution integrates a superscalar unit in a SOC, using the same set of software development tools, which makes it very easy to write code; This solution replaces the chaotic situation of incompatibility between multi-IP vendors and multiple development platforms.
• Use of standard software
• RVV is an open standard, and much of the code written for RVV will be available in the open- sources domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and commercial grade tools for compilation, modeling, debug, and trace. These standard and stable algorithms developing methods can greatly reduce development costs, allowing developers to quickly move to the market.
• Power and performance efficiency
• The flexibility and scalability of the RISC-V architecture makes it easy for RiVAI-R1 to build fit-for-purpose products for customers. The optimal system design, which is based on domain specific application (DSA), achieves the right balance of performance for the application workload within a defined power constraint. By selecting single-core, multi-core, or multi-clustered systems, the RiVAI Vector solution provides different vector/scalar/multi-core combined processor IPs on demand, helping customers achieve maximum performance efficiency while balancing their minimum area and power requirements.

Block Diagram

Applications

• Networking and Communications, industrial control.
• Advanced Driver-Assistance Systems.
• Smart wireless switch/router; data center, storage.
• Consumer Electronics, Motor Control…
• High-performance embedded

Deliverables

• RTL Evaluation
• Test Bench RTL
• Software Development Kit
• FPGA Bitstream
• Documentation

Technical Specifications