The VID_SCALER_4K IP Core is a studio quality video scaler capable of generating scaled output images up to 216 x 216 pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor and the decimation or interpolation parameters.
Internally, the video scaler is comprised of an input decimation section, a polyphase filter core section and an output interpolation section. In addition, the scaler is capable of processing two RGB pixels per clock and, as such, is able to support 4K+ pixel rates on most mid-range FPGA and SoC devices. Figure 1 shows the general architecture in more detail.
The polyphase filter core uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics if required. By default, the polyphase filter kernel uses a Lanczos2 windowed-sinc function that gives excellent all round performance.
Pixels flow into and out of the video scaler in accordance with a simple valid-ready streaming protocol3. Pixels and syncs are transferred into the scaler on a rising clock-edge when pixin_val and pixin_rdy are both active high. Likewise, pixels and syncs are transferred out of the scaler on a rising clock-edge when pixout_val and pixout_rdy are both active. In this way, the pipeline protocol allows both input and output interfaces to be controlled independently. The scaler may also be easily adapted to use standard AXI4-stream interfaces which are popular with many vendors of FPGA, SoC and ASIC devices.
