VESA DSC 1.2b Frame Buffer Compression IP
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VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
