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GDA's USB 3.0 SSIC controller is a highly configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with third party M-PHY's. GDA SSIC Controller core is architected to seamlessly integrate with either in-house developed SS Host/Device Controller cores or with standard 3rd party SS Host/Device Controller cores. It is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.<br />\n
The controller when integrated with in-house Device/xHCI Host controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as<br />\n
AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.<br />\n
<br />\n
<b>Configurable Options</b><br />\n
- Application Interface – AHB, AXI, PCIe-MPHY<br />\n
- Optional xHCI Engine with configurable number of device<br />\n
- slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc<br />\n
- Optional Device Controller with configurable number of Endpoints,<br />\n
- Types, DMA Engine and EP0 Processor<br />\n
- Number RMMI Lanes support
"""
"overview_cn" => ""
"partnumber" => "usb3_ssic"
"priority" => 1
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"productTypes" => array:1 [
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"provider.id" => 21
"provider.name" => "PRSsemicon Group"
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"provider.slug" => "prssemicon-group"
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"seofeatures" => "<ul><li>Compliant with SSIC v1.01</li><li>Compliant with M-PHY Specification v2.0</li><li>Compliant with USB3.0 Pipe Specification</li></ul>"
"seofeatures_cn" => ""
"shortdescription" => "USB 3.0 SSIC Controller"
"shortdescription_cn" => ""
"slug" => "usb-3-0-ssic-controller"
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"text_high_priority" => "usb3_ssic USB 3.0 SSIC Controller PRSsemicon Group"
"text_low_priority" => """
GDA's USB 3.0 SSIC controller is a highly configurable core and implements the functionality that can be interfaced with third party M-PHY's. GDA Controller architected to seamlessly integrate either in-house developed SS Host/Device cores or standard 3rd cores. It carefully partitioned support power management schemes which include extensive clock gating multiple wells for aggressive savings required mobile handheld applications.\n
The when integrated Device/xHCI Host has very simple application interface easily adapted on-chip-bus interfaces such as\n
AXI AHB OCP as well other off-chip interconnects making it easy in wide range of applications.\n
\n
Configurable Options\n
- Application Interface – AXI PCIe-MPHY\n
Optional xHCI Engine number device\n
slots interrupters root hub ports scratchpad optional host initiated stream data movement debug capability etc\n
Device Endpoints \n
Types DMA EP0 Processor\n
Number RMMI Lanes Compliant v1.01Compliant M-PHY Specification v2.0Compliant USB3.0 Pipe Specification.Supports Type I Port.Supports 1/2/4 Lanes.Supports PWM-G1 HS-G1/G2/G3 Rate A/B series.Implements PHY adaptor bridges between Pipe.Asynchronous clocking Bridging Layer.Configurable PIPE Interface: 8 16 32 bit.Configurable width: 32-bit.Supports Aggressive Low Power Management.Can Party cores.Can expose flexible UserApplication LogicCan by any SoC / OCB offchip – PCIeConfigurable Datawidth: 64 128 bit.Simple Register internal Access.Support various Hardware Software Configurability regarding Core characteristics.
"""
"text_medium_priority" => "USB 3.0 SSIC Superspeed Super speed interchip usb usb2 usb3 superspeed super device hub host dual mode role"
"updated_at" => 1641397379
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Usb 3.0 ssic bridge
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USB 3.0 SSIC Controller
- Compliant with SSIC v1.01
- Compliant with M-PHY Specification v2.0
- Compliant with USB3.0 Pipe Specification
