USB 3.0 SSIC IP

Filter
Filter
Compare 6 IP from 3 vendors (1 - 6)
  • USB 3.0 SSIC PHY
    • Compliant with SSIC specification 1.0
    • Compliant with MIPI-MPHY (Type-1) specification Rev 3.0-r.03
    Block Diagram -- USB 3.0 SSIC PHY
  • USB 3.0 SSIC Controller
    • Compliant with SSIC v1.01
    • Compliant with M-PHY Specification v2.0
    • Compliant with USB3.0 Pipe Specification
    Block Diagram -- USB 3.0 SSIC Controller
  • SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
  • SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC
  • SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
  • USB 2.0 PHY I/O in GF40nm
    • Compliant with SSIC specification 1.0
    • Compliant with MIPI-MPHY (Type-1) specification Rev 3.0-r.03
    • Interfaces to the USB3 Device/Host controller via the standard PIPE3 interface at 8/16/32-bit data widths
    • Customizable to supports x1, x2, and x4 LANE configurations
×
Semiconductor IP