UALink IP
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UALink PCS IP Core
- The UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification.
- Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.
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224G SerDes PHY and controller for UALink for AI systems
- UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
- As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
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UALink IP Solution
- Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
- Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
- Enables maximum throughput with up to 200Gbps per lane
- Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
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Verification IP for UALink
- API based transaction flow for ease of use
- Specification linked Protocol checks and functional coverage
- Exceptions, callback, error injection and analysis ports for Scoreboard
- TLM ports at each layer for traffic tracing
- Configurable timers for threshold testing
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112G Multi-SerDes
- Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
- Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.
