UALink IP Solution

Overview

The UALink IP solution, consisting of UALink Controller, PHY, and verification IP, is designed to meet the performance requirements for AI Accelerator to AI Accelerator connections in the scale-up of AI clusters, compliant to the upcoming UALink Consortium specification. The best-in-class IP solution provides a standards-based option for AI hardware required to scale-up high density AI Accelerator to AI Accelerator connections, supporting rates up to 200Gbps per lane. Synopsys’ complete UALink IP delivers a low-risk, standards solution optimized for power, performance, area and latency. Leveraging Synopsys’ extensive PCIe and Ethernet expertise and a proven track record in high-speed networking, AI and HPC SoC designs, designers can accelerate time-to-market and develop best in class AI hardware infrastructure, enabling a path to first pass silicon success.

Key Features

Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
Enables maximum throughput with up to 200Gbps per lane
Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
Supports high density, high radix networking infrastructure for AI workloads
Enables full hardware security needs for UALink specifications

Benefits

Maximize AI cluster throughput with up to 200 Gbps per lane
Unlock memory sharing and extend compute resources across accelerators
Speed verification time with built-in protocol checks
Reduce integration risk with complete, standards-based IP solution

Block Diagram

Technical Specifications

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