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Still Image Codec IP

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  • Baseline JPEG Codec with optional Constant Bitrate Motion JPEG Video Rate Control
    • Baseline ISO/IEC 10918-1 JPEG Compliance.
    • Additional Processing Capabilities:
    • Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard:
    • Ease of Integration.
    Block Diagram -- Baseline JPEG Codec with optional Constant Bitrate Motion JPEG Video Rate Control
  • H 265 Video Encoder IP
    • All-hardware Design (without embedded processors)
    • • High Speed (Low latency)
    • • Small Silicon Footprint
    • • Low Power
  • AV1/HEVC/AVC Single-core Encoder Video IP
    • Frame buffer compression (FBC)
    • Low delay encoding
    • Configurable IP
    Block Diagram -- AV1/HEVC/AVC Single-core Encoder Video IP
  • Unified Deep Learning Processor
    • Unified deep learning/vision/video architecture enables flexibility
    • Low power extends battery life and prevents overheating
    • Single scalable architecture
  • JPEG Codec Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
    • Full HD(YUV422)
    • 30fps@63MHz. (2Sample/clk)
    Block Diagram -- JPEG Codec Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
  • JPEG Codec Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
    • The arithmetic accuracy satisfies the requirement of compliance testing of JPEG Part2 (ISO/IEC10918-2).
    • Image Data I/O Format:Block Interleaved Format.
    • Image Size:Any size that can be divided by MCU unit.
    • Operation mode like processing mode, image size, DRI value etc. are set in internal register via external CPU.
    Block Diagram -- JPEG Codec Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
  • JPEG Codec Full HD(YUV422) 30fps@126MHz(1Sample/clk)
    • The arithmetic accuracy satisfies the requirement of compliance testing of JPEG Part2 (ISO/IEC10918-2).
    • Image Data I/O Format:Block Interleaved Format.
    • Image Size:Any size that can be divided by MCU unit.
    • Operation mode like processing mode, image size, DRI value etc. are set in internal register via external CPU.
    Block Diagram -- JPEG Codec Full HD(YUV422) 30fps@126MHz(1Sample/clk)
  • JPEG Codec 8K(YUV422) 48fps@200MHz,
    • ?Based on JPEG Extended DCT-based process/Baseline process Standards.
    • ?The arithmetic accuracy also satisfies the requirement of compliance testing of JPEG Part2 ?ISO/IEC10918-2?j.
    • ?Image Data I/O Format:Block Interleaved Format
    • ?Image Size:Any size that can be divided by MCU unit.
    Block Diagram -- JPEG Codec 8K(YUV422) 48fps@200MHz,
  • JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
    • •The arithmetic accuracy satisfies the requirement of compliance testing of JPEG Part2 (ISO/IEC10918-2).
    • • Image Data I/O Format:Block Interleaved Format.
    • • Image Size:Any size that can be divided by MCU unit.
    • • Operation mode like processing mode, image size, DRI value etc. are set in internal register via external CPU.
    Block Diagram -- JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
  • JPEG Codec 8K(YUV422) 48fps@200MHz,
    • ?Based on JPEG Extended DCT-based process/Baseline process Standards.
    • ?The arithmetic accuracy also satisfies the requirement of compliance testing of JPEG Part2 ?ISO/IEC10918-2?j.
    • ?Image Data I/O Format:Block Interleaved Format
    • ?Image Size:Any size that can be divided by MCU unit.
    Block Diagram -- JPEG Codec 8K(YUV422) 48fps@200MHz,
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