Standard cell UMC 28HPC IP
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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
