SpRAM IP
Filter
Compare
26
IP
from 1 vendors
(1
-
10)
-
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k
- Foundry Sponsored Memory Instance
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
-
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
- To offer several performance trade-offs for any memory size
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Memory generator
- SVT TSMC Bit-cell for memory core and SVT MOS for memory periphery
- Migration of a mass produced architecture already available in other geometries(90nm, 55 nm)
- Up to 30% denser than competition SRAM
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Foundry Sponsored memory generator
- Migration on an existing architecture already available for other processes (90, 85, 55 nm)
- Configuration
- SVT transistors for memory periphery
-
Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- REACH THE HIGHEST DENSITY
- Thanks to smart periphery design
- Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
- Using Pushed Rules Foundry bitcell
-
Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Source biasing implementation for low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
- Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speed)
-
Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- REACH THE HIGHEST DENSITY
- Thanks to smart periphery design
- Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
- Using Pushed Rules Foundry bitcell
-
Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Reach the highest density
- Thanks to smart periphery design
- using High density Pushed Rules Foundry bitcell
- use only 3 metal levels inside the memory
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Foundry sponsored memory generator
- Configuration
- uLL TSMC Bit-cell for memory core and uLL MOS for memory periphery
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)