SpRAM IP
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
- Available for Free Download and Use
- Reduced die cost
- Up to 15% denser than standard memory compilers
- Pushed rule bit cell from foundry
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Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Source biasing implementation for low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
- Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speed)
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Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Reach the highest density
- Thanks to smart periphery design
- using High density Pushed Rules Foundry bitcell
- use only 3 metal levels inside the memory
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
- Ultra Low dynamic power
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Configuration
- SVT MOS for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracks
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Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Reduced die cost
- Pushed rule bit cell from foundry
- Ultra low power
- Low voltage operation down to 1.2 V
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k
- Foundry Sponsored Memory Instance
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
- To offer several performance trade-offs for any memory size
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Memory generator
- SVT TSMC Bit-cell for memory core and SVT MOS for memory periphery
- Migration of a mass produced architecture already available in other geometries(90nm, 55 nm)
- Up to 30% denser than competition SRAM
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Foundry Sponsored memory generator
- Migration on an existing architecture already available for other processes (90, 85, 55 nm)
- Configuration
- SVT transistors for memory periphery