SRAM Compiler on TSMC 28nm IP
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Reach the highest density
- Thanks to smart periphery design
- using High density Pushed Rules Foundry bitcell
- use only 3 metal levels inside the memory
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1.Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2.Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
-
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
- Reduced the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
- Extend the battery life
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Configuration
- SVT MOS for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracks
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Foundry Sponsored memory generator
- Migration on an existing architecture already available for other processes (90, 85, 55 nm)
- Configuration
- SVT transistors for memory periphery
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Reach the highest density
- Thanks to smart periphery design
- Using High density Pushed Rules Foundry bitcell
- Extend the battery life
-
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Reach the highest density
- Thanks to smart periphery design
- Using High density Pushed Rules Foundry bitcell
- Extend the battery life