RegEx Processor IP
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64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
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Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- Hardware protection on processor
- Compliant with all processor families
- Escort step by step the program execution
- Protection against Cyber attack (ROP, JOP, Buffer overrun, etc.) and Fault Injection attack targeting the code execution
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32 Bit - Embedded RISC-V Processor Core
- 32 bit,
- 3-stage pipeline,
- 32 registers
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32 bit - Compact RISC-V Processor Core
- 32-bit RISC-V core
- RV32EMC instruction set
- 16 general purpose registers
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Processor Development Toolset
- A unified development model describing the processor in a single CodAL description
- High performance processor synthesis
- Complete UVM verification environment
- Advanced profiling and analysis
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Neuromorphic Processor
- Neural Processing Unit (NPU) at memory compute architecture implementing Integrate and fire neuron.
- Emulate multiple neurons with configurable Synapses.
- Compute only when events occur.
- Up-to 4 bits for weights and activation.
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32 Bit - Embedded RISC-V Processor Core
- Best-in-class performance for small-area and low-power applications
- Highly configurable and easy and quick to customize and verify
- Process compliant with ISO 26262 and ISO 21434
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Ultra-Low-Power Deeply Embedded RISC-V Processor
- Small silicon footprint for lower leakage and dynamic CPU power
- Advanced power management
- Single-issue, in-order, 2-stage pipeline
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32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions: RV32I[M][C][F][B][P][U]
- 32/16 general purpose registers
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64-bit RISC-V Application Processor Core
- High computational throughput with 7-stage pipeline and branch predictor
- Support for RISC-V single and double precision FPU
